Mengapa SRAM lebih cepat jika dibandingkan dengan DRAM?
Menurut informasi sementara, hal ini dikarenakan adanya mekanisme refreshing pada DRAM. Pada saat refreshing dijalankan, memory tidak dapat dibaca.
Mengapa disebut random akses?
RAM disebut "
random access" karena setiap lokasi penyimpanan di RAM dapat diakses secara langsung. Adalah IBM yang mempopulerkan istilah
direct access storage atau memori (RAM). Ditinjau dari sudut pandang organisasi komputer, RAM dibuat dan dikontrol agar data dapat disimpan dan diakses/diambil secara langsung ke lokasi tertentu.
http://whatis.techtarget.com/definition/0,,sid9_gci523855,00.html
Sebenarnya istilah random akses tidak mutlak milik RAM saja, karena contoh penyimpanan yang lain (seperti hard disk dan CD-ROM) juga
accessed directly (or "
randomly") tetapi istilah
random access tidak diterapkan pada bentuk penyimpanan ini.
What RAM Looks Like
In general, RAM is much like an arrangement of post-office boxes in which each box can hold a 0 or a 1. Each box has a unique address that can be found by counting across columns and then counting down by row. In RAM, this set of post-office boxes is known as an array and each box is a cell. To find the contents of a box (cell), the RAM controller sends the column/row address down a very thin electrical line etched into the chip. There is an address line for each row and each column in the set of boxes. If data is being read, the bits that are read flow back on a separate data line. In describing a RAM chip or module, a notation such as 256Kx16 means 256 thousand columns of cells standing 16 rows deep.
In the most common form of RAM, dynamic RAM, each cell has a charge or lack of charge held in something similar to an electrical capacitor. A transistor acts as a gate in determining whether the value in the capacitor can be read or written. In static RAM, instead of a capacitor-held charge, the transistor itself is a positional flip/flop switch, with one position meaning 1 and the other position meaning 0.
Externally, RAM is a chip that comes embedded in a personal computer motherboard with a variable amount of additional modules plugged into motherboard sockets. To add memory to your computer, you simply add more RAM modules in a prescribed configuration. These are single in-line memory modules (SIMMs) or dual in-line memory modules (DIMMs). Since DIMMs have a 64-bit pin connection, they can replace two 36-bit (32-bits plus 4 parity bits) SIMMs when synchronous DRAM is used. Laptop and notebook computers contain smaller 32-bit DIMMs known as small outline DIMMs (SO DIMMs).
How Data Is Accessed
When the processor or CPU gets the next instruction it is to perform, the instruction may contain the address of some memory or RAM location from which data is to be read (brought to the processor for further processing). This address is sent to the RAM controller. The RAM controller organizes the request and sends it down the appropriate address lines so that transistors along the lines open up the cells so that each capacitor value can be read. A capacitor with a charge over a certain voltage level represents the binary value of 1 and a capacitor with less than that charge represents a 0. For dynamic RAM, before a capacitor is read, it must be power-refreshed to ensure that the value read is valid. Depending on the type of RAM, the entire line of data may be read that the specific address happens to be located at or, in some RAM types, a unit of data called a page is read. The data that is read is transmitted along the data lines to the processor's nearby data buffer known as level-1 cache and another copy may be held in level-2 cache.
For video RAM, the process is similar to DRAM except that, in some forms of video RAM, while data is being written to video RAM by the processor, data can simultaneously be read from RAM by the video controller (for example, for refreshing the display image).
How Memory Access Works
Information is stored by first separating the memory area into rows and columns. The capacity of the individual chips determines the number of rows and columns per module. When several arrays are combined, they create memory banks.
The chips are actually accessed by means of control signals such as row address strobe (RAS), column address strobe (CAS), write enable (WE), chip select (CS) and several additional commands (DQ). You also need to know something about which row is active in the memory matrix at any given moment.
In today's computers, a command rate is defined in BIOS - generally 1-2 cycles. This describes the amount of time it takes for the RAS to be executed after the memory chip has been selected.
The memory controller selects the active row. But before the row will actually become active so that the columns can be accessed, the controller has to wait for 2-3 cycles - tRCD (RAS-to-CAS delay). Then it sends the actual read command, which is also followed by a delay - the CAS latency. For DDR RAM, CAS latency is 2, 2.5 or 3 cycles. Once this time has lapsed, the data will be sent to the DQ pins. After the data has been retrieved, the controller has to deactivate the row again, which is done within tRP (RAS precharge time).
There is one more technical restriction - tRAS (active-to-precharge delay). This is the fewest number of cycles that a row has to be active before it can be deactivated again. 5-8 cycles are about average for tRAS.
Memory timings are generally cited in order of importance:
http://www.tomshardware.com/reviews/ups-downs,743-3.html
How RAM Effectiveness is Measured
The amount of time that RAM takes to write data or to read it once the request has been received from the processor is called the access time. Typical access times vary from 9 nanoseconds to 70 nanoseconds, depending on the kind of RAM. Although fewer nanoseconds is better, user-perceived performance is based on coordinating access times with the computer's clock cycles. Access time consists of latency and transfer time. Latency is the time to coordinate signal timing and refresh data after reading it.
